The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of multiple patterning.
A back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing with each other and with the environment external to the chip. Self-aligned patterning processes used to form a BEOL interconnect structure involve mandrel lines as sacrificial features that establish a feature pitch. Sidewall spacers are formed adjacent to the sidewalls of the mandrel lines. After selective removal of the mandrel lines, the spacers are used as an etch mask to etch an underlying hardmask over areas exposed by mandrel removal and areas between the spacers. The pattern is transferred from the hardmask to an interlayer dielectric layer to define trenches in which the wires of the BEOL interconnect structure are formed.
Improved methods of multiple patterning are needed.